Analog Mixed Signal Verification Engineer

Requirements

• Electronic Engineering degree with 3+ years’ experience as AMS Verification AND/OR Analog or System Design experience

• Candidates should have a good knowledge of analog and mixed signal electronics, tools and flows.

• Team player with good communication skills and previous experience in delivering solutions for a multi-national client

• Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience

• Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc.

• Ability to extract simulation results, capture in a document and present to the team for peer review

• UVM knowledge would be an advantage

Responsibilities:

• Perform verification simulations and generate design documentation for complex Mixed-Signal SoC designs

• Develop behavioural models for analog blocks using SPICE or System Verilog (RNM) models (optional)

• Define and implement self-checking mixed-signal test benches in both Virtuoso Analog Design Environment or System Verilog as necessary

• Define and implement testcases and verification attributes such as checkers, stimulus and external components.

• Perform verification simulations with a mixture of models and transistor level views for the entire SoC

• Develop methodologies used to establish model vs. schematic equivalence

• Flag any functionality/performance issues early in the design cycle

• The role may also include definition and design for some sections of the SoC, predominantly digital-analog interaction

• Knowledge of  one or more of the following programming skills:  shell s, python, c++, matlab, …

• Debug test failures, follow up on design issues and drive to closure

• Regular reporting of status, completion %, activities, risks, impediments, etc

• Contribute to any continuous improvement initiatives