Desing verification engineer

Develop hardware models using SystemVerilog and verification methodologies such as UVM (Universal Verification Methodology) for infotainment systems.

Required: Excellent knowledge of Verilog and System Verilog. Experience with ing languages such as Python, Tcl, Perl. Good knowledge of C / C++, matlab

Responsibilities:

Develop test bench environment(s) and directed, random, and constrained random tests. Implement Coverage driven verification methodologies. Come up with functional coverage metrics. Develop test plans, and all necessary tools and s to write, execute and debug tests including with on-chip embedded processors, employ formal verification methods such as assertions Report progress to the rest of the verification team. Run RTL and gate simulations based on use case scenarios, and debug failures. Work with designers to achieve code coverage targets.

More benefits:

- Pension plan, meal tickets. Participation in profits, etc.